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Revision as of 16:58, 1 May 2014
Simone Campanoni is currently working under Prof. David Brooks in conjunction with Prof. Gu-yeon Wei at Harvard University. His work focuses on the boundary between hardware and software, relying on dynamic compilation, run-time optimizations and virtual execution environments for investigating opportunities on auto-parallelization. He received his Ph.D. degree with honours from Politecnico di Milano in 2009 with Prof. Stefano Crespi Reghizzi as advisor. Simone is the author of ILDJIT, a parallel dynamic compiler demonstrating principles from his thesis work. Simone started the HELIX research project in January 2010 at the beginning of his post-doc.
Timothy M. Jones
Timothy Jones is a post-doctoral researcher at the University of Cambridge Computer Laboratory, where he works within the Computer Architecture Group. Between September 2008 and August 2013 he holds a Research Fellowship from the UK's Royal Academy of Engineering and EPSRC to investigate compiler-directed power saving in multicore processors. As part of his Fellowship he worked with David Brooks and his research team at Harvard for the whole of 2010 and now works part-time with ARM.
Kevin is a PhD student in Engineering Sciences at Harvard University. His research has focused on a variability aware post fabrication technique called 'voltage interpolation'. Among his research interests are on-chip networks, GPGPU style architectures, and 3D graphics. He is advised by Professors David Brooks and Gu-Yeon Wei.
Svilen Kanev is a fresh PhD student in Computer Science at Harvard, advised by Prof. David Brooks and Prof. Gu-Yeon Wei. He is mainly interested in the intersection of computer systems and architectures. His main research intersts lie in hardware-software approaches to reliability and modeling and design of small cores. He is the somewhat proud maintainer of the XIOSim simulation suite. He did his BA degree in Computer Science at Harvard in the same research group.
Niall Murphy is a PhD student at the University of Cambridge under the supervision of Dr Robert Mullins. His research is investigating automatic parallelization of irregular programs using a combination of compile-time analysis and speculation execution. This involves mixing HELIX static parallelization with speculative execution using software transactional memory. The aim is to increase the amount of parallelism that can be exploited by relaxing the need for the compiler to generate correct code while using a runtime system to preserve.
Prof. Robert Mullins
Robert Mullins is a Senior Lecturer in the Computer Laboratory at the University of Cambridge. His research and teaching focuses on computer architecture and VLSI design. He has a particular interest in on-chip interconnection networks, chip-multiprocessors and novel parallel processing fabrics. He is a Fellow of St. John's College, where he is Director of Studies for Computer Science. He was a co-founder of the Raspberry Pi Foundation, a UK charity that promotes the study of computer science and electronics at the school level.
Prof. Gu-Yeon Wei
Prof. Gu-Yeon Wei's research group focuses on various aspects of high-speed, low-power digital and mixed-signal VLSI circuits. Significant advances in modern CMOS technology have enabled highly complex machines capable of executing extremely high levels of computation with performance doubling every few years. However, this performance comes at the cost of higher power dissipation. At the other end of the spectrum, portable electronic devices demand low-power, energy-efficient operation. Wei's research group investigates the interactions between VLSI circuits, computer architecture, and software layers to enhance energy efficiency in future computing systems.
Prof. David Brooks
My research focuses on the interaction between the architecture and software of computer systems and underlying hardware implementation challenges. These challenges include power, reliability, and variability issues across embedded and high-performance computing systems. A basic tenet of my research is that architecture design must be cognizant of these implementation issues, and that multi-layer solutions spanning circuits, architecture, and software can provide significant advantages. Addressing technology-scaling issues in a multi-layer fashion requires an understanding of the impact at the silicon level, and we have completed several prototype chip designs to meet these goals.