ISCA2014

From HELIX

(Difference between revisions)
Jump to: navigation, search
 
(One intermediate revision not shown)
Line 10: Line 10:
Data dependences in sequential programs limit parallelization because extracted threads cannot run independently. Although thread-level speculation can avoid the need for precise dependence analysis, communication overheads required to synchronize actual dependences counteract the benefits of parallelization. To address these challenges, we propose a lightweight architectural enhancement co-designed with a parallelizing compiler, which together can decouple communication from thread execution. Simulations of these approaches, applied to a processor with 16 Intel Atom-like cores, show an average of 6.85x performance speedup for six SPEC CINT2000 benchmarks.
Data dependences in sequential programs limit parallelization because extracted threads cannot run independently. Although thread-level speculation can avoid the need for precise dependence analysis, communication overheads required to synchronize actual dependences counteract the benefits of parallelization. To address these challenges, we propose a lightweight architectural enhancement co-designed with a parallelizing compiler, which together can decouple communication from thread execution. Simulations of these approaches, applied to a processor with 16 Intel Atom-like cores, show an average of 6.85x performance speedup for six SPEC CINT2000 benchmarks.
-
[ [[media:ISCA2014_Paper.pdf|Paper]] ]
+
[ [[media:ISCA2014_Paper.pdf|Paper]] ] [ [[media:ISCA2014_Slides.pdf|Slides]] ] [ [[media:ISCA2014_SlidesFF.pdf|Fast Forward]] ]

Latest revision as of 20:09, 20 June 2014

HELIX-RC: An Architecture-Compiler Co-Design for Automatic Parallelization of Irregular Programs

Simone Campanoni, Kevin Brownell, Svilen Kanev, Timothy Jones, Gu-Yeon Wei, David Brooks


Proc. International Symposium on Computer Architecture (ISCA), June, 2014


Data dependences in sequential programs limit parallelization because extracted threads cannot run independently. Although thread-level speculation can avoid the need for precise dependence analysis, communication overheads required to synchronize actual dependences counteract the benefits of parallelization. To address these challenges, we propose a lightweight architectural enhancement co-designed with a parallelizing compiler, which together can decouple communication from thread execution. Simulations of these approaches, applied to a processor with 16 Intel Atom-like cores, show an average of 6.85x performance speedup for six SPEC CINT2000 benchmarks.

[ Paper ] [ Slides ] [ Fast Forward ]

Personal tools