ISCA2014

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= Decoupling Communication From Computation Makes Non-Numerical Programs Parallelizable =
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= HELIX-RC: An Architecture-Compiler Co-Design for Automatic Parallelization of Irregular Programs =
Simone Campanoni, Kevin Brownell, Svilen Kanev, Timothy Jones, Gu-Yeon Wei, David Brooks
Simone Campanoni, Kevin Brownell, Svilen Kanev, Timothy Jones, Gu-Yeon Wei, David Brooks
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''Proc. International Symposium on Computer Architecture (ISCA), June, 2014''
''Proc. International Symposium on Computer Architecture (ISCA), June, 2014''
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Data dependences in sequential programs limit parallelization because extracted threads cannot run independently. Although thread-level speculation can avoid the need for precise dependence analysis, communication overheads required to synchronize actual dependences counteract the benefits of parallelization. To address these challenges, we propose a lightweight architectural enhancement co-designed with a parallelizing compiler, which together can decouple communication from thread execution. Simulations of these approaches, applied to a processor with 16 Intel Atom-like cores, show an average of 6.85x performance speedup for six SPEC CINT2000 benchmarks.
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[ [[media:ISCA2014_Paper.pdf|Paper]] ]

Revision as of 13:21, 21 April 2014

HELIX-RC: An Architecture-Compiler Co-Design for Automatic Parallelization of Irregular Programs

Simone Campanoni, Kevin Brownell, Svilen Kanev, Timothy Jones, Gu-Yeon Wei, David Brooks


Proc. International Symposium on Computer Architecture (ISCA), June, 2014

Data dependences in sequential programs limit parallelization because extracted threads cannot run independently. Although thread-level speculation can avoid the need for precise dependence analysis, communication overheads required to synchronize actual dependences counteract the benefits of parallelization. To address these challenges, we propose a lightweight architectural enhancement co-designed with a parallelizing compiler, which together can decouple communication from thread execution. Simulations of these approaches, applied to a processor with 16 Intel Atom-like cores, show an average of 6.85x performance speedup for six SPEC CINT2000 benchmarks.

[ Paper ]

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